Experimental assessment of Single Phase Grid assisted system using Second Order Generalized Integrator–Frequency Locked Loop

Objectives: To design and develop a simple, robust, and novel SOGI based frequency lock loop approach with DC-offset elimination capability for extracting precise phase angle of the grid voltage. As the additional objective of thework is to utilize the unused capacity of the PV system for providing reactive power support to the grid. Method: The second-order generalized integrator (SOGI)-Frequency Look loop (FLL) is implemented to achieve precise phaseangle for the control system, filtering capability for the adaptive frequency tuning aswell as an orthogonal signal generation. TheDC blocker is designed to eliminate the dc-offset generated during analog to digital conversion without compromising the dynamics of the system. To achieve the second objective, the virtual two-axis current control is simulated and experimented on in a single-phase grid-assisted system. Synchronous-frame current controllers are designed to inject active power to the grid and also ensure the unity power factor by providing reactive power support to the grid. The developed system is simulatedusingMATLAB /Simulink and implementedon the experimental stepup. Findings: The precise phase-angle is extracted from the grid voltage during the abnormal grid conditions like frequency shift, distorted by harmonics, and dc-offset. The DC-offset can be eliminated without adopting high-order FLLs by choosing the appropriate control parameter and DC cancellation block (DBC). Novelty: This study presents simple, efficient, novel SOGI based control that provides assurance of power quality as well as injection of active power injection into the grid using the virtual two-axis reference frame power control. The experimental and simulation results confirm that the presented control approach provides fast and accurate phase angle extraction in the grid synchronization with DC-offset cancellation.


Introduction
To fulfill the increasing demand for electricity as well as environmental regulation, solar photovoltaic systems (PV) become a clean and inexhaustible source of energy (1) . Nowadays, the distributed generation units are designed in such a way to utilize the additional capacity of an inverter to provide reactive support for the power factor correction or voltage regulation at the common coupling point (2) . The current control technique and grid synchronization technique of the PV system plays a crucial role to meet the interface standard with the utility (3) . The single-phase/ three-phase grid assisted systems are interfaced with grid either double-stage topology or single-stage topology. In a double-stage topology (4) , a power electronics inverter is used for active/reactive power exchange while a DC-DC converter is used to extract maximum power from the PV panel using an MPPT controller (5) . On other-side (6,7) , the power electronic converter is capable to extract maximum power as well as active/reactive power exchange in a single-stage topology. Stationary frame PLLs (8) are suitable as well as efficient in single-phase grid assisted PV converter due to the only one voltage signal to synchronize as well as an increase in the speed of synchronization in comparison with other methods. The Phase detector of stationary frame PLLs is having an inherent drawback of producing twice the fundament frequency ripple components (2ω) in the error of phase-detector (ε pd ) which further proliferates through the Loop Filter (8) . It can be minimized by adding another low-pass filter in a loop that encounters this 2ω term at the cost of reduction in bandwidth and/or phase-margin, slower transient response, and decrease in overall speed of synchronization (8) . Synchronous frame (DQ) PLLs can be adopted to compute frequency and phase angle as well as transform the grid voltage into DC signals. However, DQ PLL requires two signals i.e. a direct signal and an orthogonal signal (quadrature signal) for the computation of frequency and phase angle (9) . Therefore, an orthogonal signal is derived from the sensed grid voltage for the synchronous frame transformation by using different methods such as phase delay filters, differentiation of the input signal, Inverse Park's transform, Hilbert transform,and the second-order generalized integrator (SOGI) (10) . However, phase delay filters can cause inaccuracies to arise because of slow varying characteristics of the grid within tolerable range whereas differentiation of the input voltage signal is having an issue of noise amplification during the generation of the orthogonal signal (8,9) . The orthogonal signal generation using a Second Order Generalized Integrator (SOGI) offers bandpass filtering to eliminate the 2ω ripple without using LPFs. In a SOGI-PLL (10) , SOGI is used to create direct/orthogonal for the synchronous frame while PLL is used to estimate the frequency and phase angle of the grid voltage. However, SOGI-PLL increases computation burden for estimating frequency and phase as well as increases settling time of dynamic performance due to the two-feedback path in the SOGI PLL structure. Moreover, due to inherent resonate characteristics; the SOGI employs to auto-tune the center frequency of the grid voltage with a single feedback loop by extending the SOGI structure with Frequency Locked Loop (FLL) (11) . The SOGI structure was modified with Frequency Locked Loop (FLL) to enhance the auto-tuning capability, which is a simple and robust extension of SOGI structure. However, SOGI-FLL is not capable to eliminate dc-offset generated due to the analog to digital conversion (ADCs) of sensed voltages. In the research paper (12) , the modified SOGI (MSOGI) was proposed with the modification in standard SOGI by adding a forward gain path to get the benefit of double degree freedom for the rejection of dc-offset. However, the MSOGI with FLL becomes a third-order system as well threecontrol parameter to be a tune for the precise phase-angle detection and dc-offset rejection, which makes complexity in the implementation. Moreover, the research paper (12) also presented parallelism of the SOGI structure for harmonics elimination, but it will create more complexity for implantation as well as slow down the dynamic performance of the control system in the grid-connected application. Hence, researchers have put effort into high-ordered PLLs and FLLs (13) to achieve superior performance and dc-offset rejection by paying the cost of complexity in the implementation. To encounter the issue, Second Order Generalized Integrator (SOGI)-Frequency Locked Loop (FLL) method along with the dc-offset cancellation block are implemented to obtain superior performance without compromising the dynamics of the system as well as dc-offset rejection capability. Therefore, it can also eliminate the 2ω ripple without using LPFs and decreases computation time; subsequently, increase inherent synchronization speed as well as bandwidth as compared with convention PLL. In addition to the above work, this paper also an insight into active-power generation and reactive power compensation. The power factor deterioration (13)(14)(15)(16)(17)(18) can be avoided by the presented control approach during the active/reactive power operation. The single-phase grid-assisted PV system is designed to inject power in the low voltage distribution network without exceeding voltage and harmonics limits as defined EN50160 and IEEE 1547 standards.
This paper mainly focuses on robust control of active and reactive power in the grid-assisted PV system using the SOGI based current control techniques and the SOGI-FLL as a grid synchronization technique. This paper is presented in five sections. Sections 2 describes the control strategy of grid-assisted PV systems including all key blocks like grid synchronization, dcoffset cancellation, voltage controller, and current controller. It also gives insight into the active/ reactive power control through a power electronic converter. Section 3 shows the experimental results of the grid-assisted PV system. The comparative study is discussed in section 4. The conclusive remark is written in section 5.
https://www.indjst.org/ 2 Control strategy of grid assisted PV system Figure 1 illustrates the schematic of grid assisted PV system. The grid assisted PV system performs conversion of DC power of PV panel to AC power, which is finally dumped into the grid. The control system of grid assisted PV system consists of (i) MPPT based outer voltage controller for the active power injection into the grid,(ii) reactive power control outer-loop (iii) grid synchronization using the SOGI-FLL, (iv) the SOGI based current controller, and(v) synchronous frame transformation and the SPWM block. The virtual two-axis synchronous reference frame current control techniques provide reactive power support to the grid for unity power factor at the common coupling, as shown in Figure 1. The perturb and observe (P&O) algorithm is an iterative method to extract maximum power from PV panel and is used here (13) . It is simple and well-known and presented in many research articles. However, this algorithm never reaches MPP but oscillates around it. It can be minimized by reducing the perturbation step size at the cost of slower MPPT. Many articles have been published on the modelling of the PV panels and MPPT algorithm. Hence, they are briefly discussed in this paper.

Structure of Second-Order Generalized Integrator (SOGI)
The structure of SOGI, as shown in Figure 2, and their transfer functions in equations (1) & (2) are indicating that two imaginary complex conjugated poles placed at ± jω 0 that behaved like a resonator oscillating at an angular frequency ω 0 . This feature offers infinite gain at resonator oscillating at the angular frequency, ω 0 as observed from the bode plot of SOGI in Figure 1(b) that can be useful in the implementation of voltage controlled oscillator (VCO) block in PLL. The transfer functions of SOGI are given as: https://www.indjst.org/   (4) with ω 0 = 2π.50 rad/s, respectively, that increase the amplitude of output signals which cause an unstable system, when a unitary step is applied as input. To prevent the system to be unstable, the input to the SOGI structure is modified as weighted k of (where k is the gain parameter of the SOGI) the difference of input signal which is nothing but grid voltage v in (s)and unity feedback of output signal Y(s) to the input as shown inFigure 3. The transfer functions D v (s) and Q v (s) are rewritten as: Bode Diagrams describe band-pass compatible nature of the output Y(s) (Figure 3 (b)) and nature of the output Y'(s) as lowpass compatible, while phase responses of curves at frequency 50Hz are observed at 0 • and 90 • respectively which indicates that Y(s) is having 90 • phase lead to Y'(s) (Figure 3 (c)). Moreover, the magnitude responses of Bode are maintaining 0 dB at the 50Hz fundamental frequency and attenuating amplitude at 5 th and 7 th harmonics frequency i.e.250Hz and 350Hz. It is seen from Figure 3 that the transfer function Y(s) and Y'(s) can extract only fundamental components of grid voltage while eliminating harmonics components of grid voltage as a second-order band-pass filter. https://www.indjst.org/

Frequency locked loop
However, SOGI has an inherent resonate character that can use as a voltage-controlled oscillator, which emphasizes to design a simple and robust single feedback control loop for an auto-adapting center frequency of the SOGI resonator as per the input grid frequency. Frequency Locked Loop, FLL is nothing but the simple and robust extension of the SOGI structure as shown in Figure 4 (a). In order to make auto-tunable SOGI-QSG, it should pay attention to the voltage error signal E v (s), which is nothing but the difference between the input v in (s) and output Y(s) and behave as a notch filter with zero gain and180 o phaseangle jump at a center frequency as observed from the bode diagram in Figure 4(b), is described in term of the transfer function by Figure 4 (b) presents the dc blocker for eliminating the dc-offset generated due to the analog to digital conversion (ADCs).
The transfer function of E v (s) and Q v (s) gives worthy information for an auto-tunable frequency control system by taking a common bode diagram of the transfer function E v (s) and Q v (s), as depicted in Figure 4(c). The Bode diagram of transfer functions, E v (s) andQ v (s), reveal that the phase of signals E v (s) and Q v (s) are in a phase when input frequency (ω) lower than the SOGI resonance frequency (ω ′ ) i.e. ω < ω ′ and out of a phase (180 o phase difference) when ω > ω ′ , as indicated in  Hence, a frequency error variable ε f is derived from the product of E v (s) and Q v (s), which remain positive when input frequency (ω) is lower than the SOGI resonance frequency ( ω ′ ), zero when ω = ω ′ , and remain negative ω > ω ′ in the SOGI-FLL. Moreover, the frequency-locking loop (FLL) can be designed by using frequency error variable, ε f , and a negative value of frequency loop controller gain,−γ as shown in Figure 4 (a). The frequency loop controller gain (−γ ) is used to achieving DC component of the frequency error variable ε f equal to zero by changing SOGI resonance frequency, ω ′ , until equal to the input frequency, ω. A feed-forward variable, ω c i.e. nominal value of grid frequency is provided in the frequency locking loop(FLL) to speed up the initial synchronization process. The SOGI-OSG and Frequency locking loop combined a structure diagram known as SOGI-FLL for a single-phase grid synchronization system, as shown in Figure 4. The transient and steadystate behavior of the SOGI -FLL mainly depends on a suitable value chosen for control parameters γ and k in order to obtain the desired response in the estimation of the frequency and amplitude of the input signal.

DC-offset cancellation block
The dc-offset presents due to the analog to digital conversion(ADCs) and signal conditioning and the SOGI structure is inefficient to eliminate the dc offset as observed from the bode diagram, shown in Figure 3 (b). The Bode diagram of the SOGI presents the inability to attenuate low-frequency components especially the dc signal from the grid voltage. It is very well common that integration of DC value yields steps signal, further integration produces a ramp signal. The presence of a DCoffset in the sensed grid voltage deteriorates the performance of a SOGI. The conversion of the continuous-time input signal into digital values generates an error, commonly known as quantization error. This error arises due to the input signal by a fixed number of digits in the ADC conversion process. If a normalized sinusoidal signal (i.e. amplitude varies between +1 to -1) is to be converted into digital ADC, it employs (b+1) bits including sign bits. The number of levels and quantization step size is 2 b+1 and 2 2 b+1 = 2 −b respectively. The quantization error is experienced due to rounding, which is the process of reducing the size of a binary number of a finite word size of b bits such that the rounded b-bit number to closest to the original un-quantized input signal. The quantization error, e (n) is given by Where x q (n) and x (n) are the sampled quantized value and the sample un-quantized value of the input signal to the ADCs respectively. Due to the rounding, the error signal obeys the following relations: −q 2 ≤ e(n) ≥ q 2 . In signal processing, a quantization error is commonly viewed as an unwanted discrete noise signal. Therefore, the output signal from the ADC is the sum of input signal x (n) and error signal e (n) as described in equation (8). The variance or power of the error signal e (n) is given by: Here, E(e (n)) is the mean value of e (n) and it is zero while E ( e 2 (n) ) is the average value of e 2 (n) and p (e) is the probability density function.
The average value of e 2 (n) is mathematically described as: The output signal of an ADC converter is passed through a first-order filter and described by Besides, the transfer function of the system and impulse response of the system is given as: ; h(n) = a n u(n) The steady-state variance of a noise or quantization noise presents in the input signal is given as https://www.indjst.org/ Generally, digital signal processors have 10-bit or 12-bit ADCs. To eliminate the steady-state variance or quantization noise in the input signal, a is preferably chosen from the range 0.5 ≤ a ≤ 0.99 (ideally a lies between 0 <a<1 to remain Region of convergence (ROC) inside the unit circle for the stability). Assume a=0.98 and 12-bit digital signal processor, the quantization noise at the output of the filter is 4.2088e-22≈ 0.

PV inverter control
The active power injection is controlled by DC voltage controller as shown in Figure 1 .The PV voltage (Vdc) is sensed through the hall sensor and given to first-order low pass filter to block switching ripples. The DC voltage reference is generated by MPPT algorithm as shown in Figure 1. The difference of DC reference voltage and actual voltage is fed to a PI controller to extract maximum power from PV panel. The voltage error of DC link ( △v dc, err ) in nth sampling instant is described as: The direct/ orthogonal component of current is created from the sensed grid current. The i d and i q are computed by the dq transformation. The error signal is generated by taking the difference of reference currents (i.e. i d,re f andi q,re f ) and computed i d andi q , which is further given to PI controller to generated duty cycles of the inverter (i.e. m d and m q ) The active current reference of the inverter at the n th sample is given as: The reactive current reference of inverter at n th sample is given as: The duty cycles (m d and m q ) of PV inverter at n th instant are represented as: Here, K p1,dc and K i1,dc are proportional gain and integral gain of DC voltage controller respectively. K p2,dc & K i2,dc are proportional gain and integral gain of reactive power controller respectively. In the inner current loop, K p,inner and K i,inner are proportional gain and integral gain of dq-axis current controller. Using the inverse park transformation, the modulating signal is generated as For the SPWM techniques, v β is given as modulating signal and represented as: If PV inverter only performs active power injection at that moment, m q is zero and v β is given as The SPWM technique is used to generate gating signals for the power electronics switches and the inductor filter use as a bridge between the power electronic converter and grid.

Delay compensation block
Due to the computation of the control approach, it will inherently afford unit sample delay between the computed reference signal and actual signal. Indeed, the converter reference signals that are computed at the kth sample are given to the converter at the beginning of the (k+ 1) th sample. This inherent computation sample delay degrades the performance of the control approach.
To compensate the computation sample delay, converter reference signals at the (k+ 1) th sample is predicted from the reference signals at the present sample i.e. kth sample and past sample i.e.(k-1)th sample, as presented in the eq. (16). https://www.indjst.org/

Experimental Results
The SOGI-FLL is implemented and tested by using a downscaled STM32F407VGT6 microcontroller and waijung blockset environment in the Simulink/MATLAB. The discrete-SOGI-FLL model is converted into c code, that further, compiled and dumped into microcontroller by KEIL-IDE (KEIL 4 and above, ST-utility driver) and physical interface USB cable. The STM32F407VGT6 is a low-cost, 32-bit microcontroller having two digital-analog converters (12bit-DAC) with 168 MHz crystal frequency, and supported by the waijung environment (i.e. model-based programming) in the SIMULINK/MATLAB. The convenient parameter value of the SOGI-FLL are chosen as k = 0.5,γ = −5000, sampling time t s = 50 usec, and the grid voltage frequency f g = 50 Hz. The DC-offset is generated due to the ADC conversion block and other discrete blocks cause uncertainty in the phase-detection of the SOGI -FLL. However, many researchers presented many improved structures of the SOGI-FLL. The SOGI-FLL was used along with a first-order infinite-impulse response (IIR) filter (i.e. known as DC blocker) to eliminate a DC offset without moving toward a complex modification in the structure. For the validation, SOGI-FLL is tested under the various cases individually in the experimental set-up as follow: Test 1: It is conducted on the grid voltage affected by voltage sag of 0.6 p.u. and 5% of a DC-offset. Test 2: It is conducted on the grid voltage experiences a -5 Hz frequency step change (i.e. frequency jump (50Hz to 45Hz), phase-angle shift (0 0 to45 0 ) and 5% of a DC-offset.
Test 3: It is conducted on the grid voltage affected by harmonics and 5% of a DC-offset. In Figure 5, experimental results are obtained to measure the settling time of the SOGI-FLL on the grid voltage affected by a voltage sag of the magnitude 0.6 p.u at t=200 msec. These results are only visible in the digital oscilloscope has a frequency above 70 MHz and change must be applied after 200msec. Figure 5 shows that v α /v ′ of SOGI-FLL settled down before the third cycle i.e 50 msec when grid voltage affected by sag of 0.6 p.u. and 5% of a DC-offset. As shown in Figure 6, the dynamic response of SOGI-FLL is evaluated by performing experimental test-2 i.e. grid voltage experiences a -5 Hz frequency step change (frequency jump from 50Hz to 45Hz) and phase angle shift (0 0 to 45 0 ) at t =500msec. The phase-angle shift (from 0 o to 45 o ) is intentionally made only to observe frequency change occurs at t =500msec, as shown in Figure 6. The frequency and phase-angle detected by the SOGI-FLL are settled down before the second cycle observe from the time instant at which the frequency shift is made in the grid voltage. Due to the unavailability of AC grid simulator, test-3 is conducted by generating sin wave inside SIMULINK/MATLAB and frequency controlled by externally through the ADC pin of a microcontroller. As shown in the Figure 7, the dynamic response of SOGI-FLL is evaluated by performing experimental test-3 i.e. grid voltage affected by 3 rd , 5 th and 7 th order harmonics with proportional amplitudes of 35%, 15%, and 8%, respectively, concerning fundamental grid voltage. Besides, the SOGI-QSG is experimentally proven as band-pass filter through the output signal of SOGI-FLL i.e. v α /v ′ and v β /qv ′ free from the effect of harmonics distortion as shown in Figure 8. The SOGI-FLL works in the same fashion even in the situation when the grid voltage is affected by multiple abnormalities. An experimental setup of a grid-assisted PV system implemented using a single-phase IBGT based power converter card, an IGBT driver card with short-circuit protection, https://www.indjst.org/ STM32F407VG 32-bit DSP based microcontroller, current and voltage Hall sensor for DC side, current transformer (CT) and power transformer (PT) for ac side along with the features of DC offset adjustment for uni-polar ADC in a microcontroller, line inductor, 2 series-connected PV panel strings, and step-up transformer interface between PV system and the utility grid. The experimental results are obtained by using the experimental setup of a grid-assisted PV system with the specification mention in Table 1. Figure 8 shows the experimental result of grid voltage and inverter current during various conditions (i) No-load conditions, (ii) inductive load connected at common coupling point, and (iii) load connected at the common coupling point.  Figure 8(a) presents that active power injected into the grid as well as grid voltage and inverter current is out of the phase.

Discussion
In very recent years, some attempts for designing high-order frequency-locked loops (FLLs) have become common practice for the elimination of dc-offset. Nevertheless, the merits and demerits of these structures, particularly in comparison with a SOGI-FLL and high-order PLLs, are rather unclear. The high-order PLLs and FLLs knowledge provides fast and accurate phase angle extraction by paying the cost of hardware implementation complexity. Many researchers put efforts into the implementation of the SOGI-FLL in the single-phase grid-assisted PV system, but none of the above have focused on the impact analysis of parameter k and γ and their effects in the transient and steady-state response SOGI-FLL. The dynamic performance of the frequency estimation in the SOGI-FLL is examined by experiencing a -5 Hz frequency step change (i.e. frequency jump (50Hz to 45Hz) and phase-angle shift (0 • to 45 • )at the 200msec with the feed-forward taking the initial frequency value i.e. 2π * 50. In Figure 9 Table 2. The parameter k is used to amplify signal (ε v ), which affects the transient response and bandwidth and of the SOGI-FLL. The selection of the gain k is compromising between good signal filtering and the dynamic response of the system (Figures 3 and 9). The selection of the γ value is a trade-off between the precision of the frequency estimation and dynamics of the SOGI-FLL. Narrower bandwidth increases the rise time (t r = 0.35/ BW), further, degrades the successive value stabilization of frequency estimation, however, adversely improves the other parameters. The SOGI-FLL has superior performance over the other grid synchronization techniques except for DC-offset elimination. The DC-offset cancellation block before the SOGI-FLL eliminates the DC-offset without degrading the performance of SOGI-FLL. The delay compensation block improves the dynamics of the control approach to ensure the power quality at the PCC. The notable contribution in this paper can be summarized as follows: 1. SOGI-FLL has proven its ability to eliminate dc-offset generated due to the ADC conversion by adding DC blocker without increasing the tuning complexity of the control parameters in the SOGI-FLL. 2. The appropriate selection of control parameter in the SOGI-FLL improves synchronization speeds during the grid abnormality, increases robustness against input noise and disturbances, and estimates accurate and non-distorted values phase-angle for the control system. The impact analysis of parameter k and γ and their effects in transient and steady-state response SOGI-FLL. 3. The single-stage single-phase grid assisted PV system performs active power-sharing as availability of solar energy with reactive power compensation to achieve unity power factor at the utility.

Conclusions
In this study, attention was paid to estimate the frequency and further phase-angle detection by the SOGI-FLL method for changing the frequency and voltage of the single-phase utility. To this end, SOGI-FLL implementation with dc-offset cancellation block is presented for enhancing the capability of fast and precise phase-angle detection, harmonics and dc-offset rejection. It is confirmed by experimental and simulation results that there is no need to choose high-order FLLs or PLLs for the dc-offset rejection. Moreover, simulation assessment is also proven that the appropriate selection of control parameters is a trade-off between the dynamic response, filtering capability and the desired accuracy in detection of frequency and phase angle especially during non-ideal grid conditions for single-phase grid-tied inverter. The Virtual two-axis reference frame (SOGI based) power control for the single-stage grid-assisted PV system was implemented by utilizing an additional capacity power electronic converter to provide reactive power support to the grid. During a no-load condition, the PV inverter is only dumping active power into the grid. The PV inverter is behaving as inductive during capacitive load connected whereas capacitive when inductive load connected to common coupling point, as confirmed through experimentation.