FPGA Implementation of a Novel Two-internal-State Memristor and its Two Component Chaotic Circuit

Objectives: To propose a second-order locallyactive memristor, a twocomponent chaotic circuit resulting from this current-controlled generic memristor and an application in steganography. Methods/statistical analysis: Using a one-state-variable first-order memristor, a model is proposed which is obtained bymodifying a locally-activememristor based on a current-controlled genericmemristor. Themodel has two internal state variables: a voltage stored up in a capacitor and a current stored up in an inductor. With an external inductor, 3D-two-component chaotic circuit is developed. Numerical studies are made using MATLAB and confirmed by a field programmable gate array (FPGA) based hardware implementation. Findings: A two-state-variable based second-order memristor model is presented. The novel memristor configuration leads to the design of a simple two-component chaotic circuit. By investigating the characteristics of the memristor, it is shown that the memristor can be switched from a predominantly passive region to an active region with a wide locally-active region. An application in steganography helps to hide a secrete message inside an image. Application/improvements: The results obtained in this investigation will enrich the literature of memristive circuits, enhance the simplification of chaotic circuits and can be used to improve the memristive circuit based applications inmany research domains such as secure information in telecommunications, Random Number Generation (RNG) and image encryption.


Introduction
A number of important applications would benefit from the design and implementation of a locally-active memristor, which is defined to be any memristor that exhibits negative https://www.indjst.org/ differential memristance or memductance for at least a current or a voltage applied to the memristor (1) . This is one of the drives of this research work, to realize a locally active memristor that has a wide locally active region characteristics and for some parameter values or frequencies of excitation is entirely active. Recently, the investigation of memristor chaotic circuits and systems is a hot issue and many researchers are delving into such studies and many applications are being derived from memristor based chaotic circuits (2,3) .
Even though memristors have a promising future, solid-state samples are still unavailable and this constitutes a problem to researchers. Thus, there have been many initiatives to develop memristor emulators and to study their behavior and the possible applications (4,5) . The emulation circuits are built to mimic the behavior of the memristor based on the modeling equations.
The analog memristor emulators are usually built using analog commercial off-the-shelter components (6) . This is inefficient for large scale applications that require a huge number of memristors such as neural networks. On the other hand, FPGA implementations of the memristors are much more advantageous because they are easily programmable, reconfigurable, controllable, precise and exhibit better performance (6) .
Due to the unique electrical performances of the memristor, 3-element or N-element memristive circuits, especially the chaotic circuits, have been widely explored and reported in recent years. Muthuswamy and Chua in 2010 (7) observed chaos with an autonomous chaotic circuit that uses only three elements: a linear passive inductor, a linear passive capacitor and a nonlinear active memristor. The circuit was modelled by a system of three differential equations. As of 2010, it was the simplest chaotic circuit in literature. In 2012, Tchitnga et al. (8) showed evidence of chaos in an autonomous Hartley Oscillator made simply of a JFET and a tapped coil. The authors modeled the system by four differential equations. In 2017, in a paper titled: "A simple meminductor-based chaotic system with complicated dynamics", (9) the authors proposed a three component chaotic circuit made up of a resistor, a capacitor and a meminductor connected in parallel. The circuit is modeled in a three differential equation system and shows complicated dynamics. Many more strives have been made of recent in an effort to simplify chaotic systems in terms the number of elements used in the circuit (10)(11)(12) . Recently, researchers are using not just the properties of memristors, but memory devices (memdevices) to reduce the number of elements in a circuit that are required for chaotic oscillations (13) . This push has been ramped up with the advent of these memory devices.
A number of memristor models have been developed and their circuit emulators, however, most of these models are firstorder and utilized only a one-state-variable. This is a simplification which is not adequate for accurate modeling.
In this work, we exploit the "actual simplest chaotic circuit" proposed by Muthuswamy and Chua in 2010 to develop a much simpler chaotic circuit made up of two components (the memristor and an inductor) and modelled by three differential equation having two nonlinear terms. Our memristor model has two internal state variable, its memristance can be positive, zero and negative, has a wide range for local activity and will act like the memristor model in (7) for some parameter values. Since our model has two state variables, we require just a single variable to satisfy the condition for the system to be chaotic. This third variable is made available by a passive linear inductor which is added to our memristor model. The hardware implementation of this generic charge controlled memristor and the two component chaotic oscillator is designed utilizing analogue circuitry and FPGA.

Circuitry and mathematical model
In (14,15) , all memristors are classified into three classes including the ideal memristor, the generic memristor and the extended memristor and presented the mathematical definitions of memristors. The ideal memristor is the simplest and most practical model. The ideal memristor models developed by the HP Lab is widely used but does not fit the anticipated nonlinear behaviors of a real memristor. The extended memristor is an extended form of ideal memristor and Chua generalized the memristor concept to a much broader class of nonlinear dynamical systems and named it as memristive systems (16) . The mathematical definition of generic memristor model is given below.
This is for a generic current -controlled memristor, representing the state-dependent Ohm's Law equation and the state equation. y is an n-dimensional vector of the internal state variables and dy/dt is the time derivative of the state vector. In (7) an active generic memristor is defined where n = 1; a voltage stored up in a capacitor inside the memristor.
The circuit design and implemented memristor is given by the equation below: Where: i L1 = −i M . i L1 is the current through the external inductor used to measure the current entering memristor as seen in (7) . This represents the Muthuswamy-Chua memristor model, which is a single state (first order) locally active generic memristor.
To obtain a two state (second order) generic memristor, we introduced another state variable by connecting an inductor in parallel with the capacitor C M in Figure 1, (we produce a tank circuit represented by RSTU). This second state variable is a current which is stored up in the inductor, L M .
In the modified memristor, the first part of Eq. (2) is maintained, and the equations for the dynamics of the states of our model is obtained by applying KCL at the junction A and KVL round loop RSTUR to obtain Eq. (3): So our model of the memristor has two internal variables: (i) the voltage across the capacitor C M and (ii) the current through the inductor L M . This makes it a second order memristor.

Transforming the Circuit Equations to System Equation
Let us choose the non-dimension time: . To excite our memristor circuit, a sinusoidal current given by (4) is used.
where the real frequency in Hz, f = f d R a C m and the amplitude of the current in amperesis: 1 and the initial conditions: y(0) = 0.1, z(0) = 0.1 , we investigate the fingerprints of this memristor model.

Memristor Characteristics
The next step is to prove that our model satisfies the definition of a memristor or memristive system and also verify the local activity of our memristive system.

Pinched Hysteresis Loop of the Memristor
Any two-terminal device exhibiting a pinched hysteresis loop which always passes through the origin in the voltage-current plane, when driven by any periodic input current source, or voltage source with zero DC component, is called a memristor (14) . Thus, the pinched hysteresis loop is always used as the characteristic fingerprint to identify the memristor (17) . Moreover, the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity (18) . Figure 2 shows the pinched hysteresis loops of the above generic memristor at different frequencies when it is driven by a sinusoidal current with an amplitude of 1mA. Figure 2 , we observe that the pinched hysteresis loop of memristor shrinks to a single-valued function as we increase the frequency of input current. Notice that Figure 2(b) shows that the memristor has negative memristance region and also degenerates into a linear negative memristance for frequencies greater than or equal to 10 kHz. The figures have been plotted separately for the purpose of clarity; they can actually be plotted on the same graph. However, the larger amplitudes at lower frequencies will dwarf the curves at higher frequencies. https://www.indjst.org/ It also worth noting that the nature of the hysteresis loops is also dependent on the parameters of the memrsitor. In Figure 3, with changing values of the parameter P, at fixed amplitude (1mA) of excitation and fixed frequency (0.5 kHz), the area of the hysteresis loops decreases with decrease in the value of P and also switches from predominantly passive to the active region. With values of P less than or equal to 0.1, the loop degenerates into a linear negative memristance.
As we know, the pinched i-v hysteresis loops called fingerprints provide necessary and sufficient conditions for identifying whether a device is a memristor or not. But the most general memristor identification scheme is the Coincident Zero-Crossing Signatures, i.e. the waveform of the current v(t) associated with the voltage i(t) measured from a current-controlled memristor must cross the time axis whenever i(t) = 0. However, observe fromFigure 3(b) that the zero-crossing points of v(t) include not only all zero-crossing points of i(t), but also several additional zero-crossing points when i(t) ̸ =0, which are shown with the little black dots.

DC I-V Loci of the Memristor
The DC Voltage-Current characteristic (DC I-V loci) is a smooth curve consisting of a set of points and a sufficient test to claim that the memristor is locally-active (13) . These points of DC I-V loci can be derived in steps (19) depending on the Eq. 5 and the Ohm's laws dependent equation.
To derive the dc characteristics, we set:ẏ = 0,ż = 0 in (5) since by definition at DC all derivatives are zero. We solve for the internal state (y) of the memristor in terms of the current (worth noting that y is a function of z).
where: Ω = γK 1 K 2 . This parameter brings in the contribution of the second state variable z. Substituting for y in the Ohm's law dependent equation, we obtain: Using the parameters: α = 1, β = 1, P = 1, Ω = 1 , a plot of the (I m -V M ) is shown in Figure 4 with the locally active region highlighted. In Figure 4, we observe that the memristor system given by (5) is locally active. The same analysis method about locally-active memristor is used in (20) and (21) . We observe from the graphs that the parameters introduced by the second state variable greatly influence the characteristics. For, Ω = 0.0 we obtain the Muthuswamy-Chua system and I-V characteristic as shown in (7) . To obtain the exact graph, we set α = 0.2 and β = 1.7 to obtain Figure 4(a). https://www.indjst.org/

Novel Two Component Memristive Circuit
Based on the memristor model defined by the equations above and the poof of the characteristic signatures, a new chaotic oscillator is designed as shown in Figure 5. Its peculiarity is the fact that it has only two components: a memristor and an inductor. The inductor provides one state variable whereas the memristor provides two state variables. Hence we get a total of three state variables, the minimum required for chaotic behavior in a continuous time smooth dynamical system

Circuit equations and mathematical model
From Kirchhoff 's circuit laws, the following differential equations are obtained which govern the dynamics of the circuit.
Using the same transformation and time scale as above, we obtain equation (9), where: We choose our parameters such that: B = 5; β = 1; R = 0.01; P = 0.5; α = 1; γ = 1 ; With these parameters and considering that R is small and does not affect the dynamics of the system, the system (8) becomes: The system given by Eq. (9) has one cubic nonlinearity and one quadratic nonlinearity, making it a simple system in terms of mathematical representation. This complements the fact that our system is indeed the simplest chaotic system; just two circuit components and two nonlinear terms. Using the initial conditions as: x(0) = y(0) = 0.1, z(0) = 0.0 and the parameters above, the Lyapunov exponents can be calculated as: LE 1 = 0.165, LE 2 ≈ 0.00, LE 3 = −0.258 , using the algorithm proposed by Wolf et al. (22) . This means that the system is chaotic. The phase portraits of system (9) are investigated by numerical simulation as shown in Figure 6. The projections of phase portrait on z-y, y-x planes are shown in Figure 6(a) and 6(b) respectively. From the numerical simulation results we know system (9) can generate a chaotic attractor.

Equilibrium Point and Stability
To analyze the system, a good start is to find its equilibrium(s), and then to characterize the local dynamical behaviours of the system orbits near these point(s). Distribution and local dynamical characteristics of the equilibrium(s) greatly influence the nonlinear dynamics of the system. https://www.indjst.org/ By solving the equilibrium system obtained from (9), we obtain 3 equilibrium points given by: The Jacobian matrix of (9) with the parameters defined above is given by: The stability of equilibrium point can be judged by the eigenvalues of the characteristic equation det (λ I − J) = 0. The eigenvalues of the first equilibrium point are given by: λ 1,2 − 0.55 ± 0.89i, λ 3 = 0.00 + 0.00i .This shows that the equilibrium point E 0 is a stable point. For the second equilibrium point E 1 , the eigenvalues are given by: λ 1,2 = 10.50 ± 0.86i, λ 3 = −0.10 . The eigenvalues of the third equilibrium point E 2 are given by: λ 1,2 = 3.17 ± 10.05i, λ 3 = −0.10 . From the solutions of E 1 and E 2 , there is one real eigenvalue and a pair of complex conjugate eigenvalues (a so-called index-2 saddle-focus), which are the criteria to generate a chaotic attractor (23,24) .

FPGA Implementation of the Memristor Model and the Memristor-Based Chaotic Circuit
In this section, we are going to implement practically the proposed memristor model and the memristor-based chaotic circuit using an FPGA development board instead of an analogue discrete circuits as usually seen. The FPGA we are using is robust, portable and re-configurable. It overcomes weaknesses of analogue devices (sensitivity to temperature, sensitivity to initial conditions, etc.). With FPGA implementation, we have some flexibilities such as setting control parameters, frequency and initial conditions accurately, reducing the system to a portable source code, realizing complicated mathematical operations or algorithms. These benefits increase the number of realizable memristor chaotic circuits (25) , making the implementation process simple and accurate. In this work, the forward Euler method is used because of its execution speed and its low cost in term of FPGA resources needed (26,27) . The proposed memristor model (5) and the memristor-based chaotic circuit (9) are discretised as follow: x n y n+1 = y n + h (−Px n − αy n + y n z n − γz n ) The step size of h = 0.001 is chosen to achieve a better accuracy. The calculations in the hardware implementation is done using 32 bits floating point of the IEEE754 standards then converted into signed-fixed. The outputs are adjusted to extract only the decimal part of the signed-fixed value then converted into standard logic vector. The dynamic state of each sample is sent out into GPIO ports of the FPGA board. The discrete state of the equations (5) and (9) are directly describe using VHDL into Quartus II 10.1 design software and the behavioral simulation is performed with ModelSim-Altera 6.5e. The Altera chip of type Cyclone IV E EP4CE115F29C7N is chosen as target device. The Register Transfer Level (RTL) schematic presented in Figure 7(a) is the top-model of the implemented the proposed memristor model and the RTL schematic presented in Figure 7(b) is the top-model of the implemented memristor-based chaotic circuit. Pin X and Y correspond to the current (i) and the voltage (V) respectively for Figure 7(a) and Pin X, Y and Z in Figure 7(b) correspond to current through the inductor L 1 , the voltage across the capacitor C M and the current through the inductor L M respectively.
https://www.indjst.org/ The practical demonstration of the feasibility of the proposed memristor model and the memristor-based chaotic circuit are done through the FPGA implementation shown by the set-up in Figure 9. Two R/2R resistors ladders are used as digital to analog converter (DAC) and connected to the GPIO ports of the DE2 115 FPGA board. The resulting analog signals are then filtered using capacitors. The filtered signals are then connected to the probe of oscilloscope to visualize the portraits. Figure 8 shows the experimental relationship between current and voltage for the locally active memristor with varying frequency of excitation. We observe that the loops switching from the predominantly passive region (a, b, c) to the active region (d, e, f) for frequencies: f = 0.2 KHz, f = 0.3 KHz, f = 0.4 KHz, f = 0.85 KHz, f =1.0 KHz and f =10.0 KHz. We also notice that for increasing frequencies, the pinched hysteresis of the memristor shrinks to a single valued function for f = 10 kHz. https://www.indjst.org/ With the initial conditions, and the parameters used in the numerical simulation, we obtain the experimental phase portraits of the two component chaotic system given by Eq. (9) as shown in Figure 9(a) and (b) representing the phase portraits in the z-y and y-x planes respectively. As one can see the results obtained from the practical implementation are in accordance with the numerical simulations.

An Application in Steganography
In this section, we proposed a method to hide a secret message inside an image using steganography and chaos encryption. Steganography deals with the art of hiding information with an interesting property of hiding the mere existence of the secret information (28) . Steganography is different from cryptography. Cryptography is the practice of scrambling a message to an obscured form to prevent others from understanding it while steganography is the study of obscuring the message so that it cannot be seen (28) . To make a steganography we require generally two files: the cover/carrier file and the secret file. However, many multi-media carriers like, video, audio, image, text, etc. can act as a cover media to carry the secret message. Here, we used an image and test file as cover file and secret message respectively.
Many algorithms and procedures, such as Least Significant Bit (LSB), have been written to hide text in an image. (29,30) LSB method allows to start by passing both secret message and cover image into the encoder. The LSB embeds the secret message encrypted in the least significant bits of pixel values of the cover image. The secret message is encrypted using an affine cipher based on the two component memristor chaotic system. This with the support of the date of birth (DOB) keys. DOB key enables to construct a key using birth day, month, and year of the sender and receiver. The Figure 10 shows us the scheme of our proposed method.
https://www.indjst.org/ We performed an encryption of secret message before performing the steganography. This enables us to have a good integrity of our message between the sender and receiver.

Affine cipher based on the two component memristor chaotic system and DOB
Ciphers convert the message by a rule, known only to the sender and the recipient, which change each individual letter (31) . An affine cipher is a combination of shift and multiplication cipher. E(.) and D(.) respectively the encryption and decryption processes of affine cipher. For given message M, E(.) and D(.) are defined in (31) by: Where: l, m are parameters of affine cypher key k(k = (1, m)) , l' is inverse of 1 modulo p and p is a positive integer.
To apply this method, we considered S and R in our cryptosystem as sender and receiver respectively. To exchange a secret message, S and R have to generate their own secret key pair using DOB and fractional order hyper chaotic system. Consider D = (D 1 , D 2 ) be a pair of DOB of S and R who only shared between them. D 1 is DOB of S and D 2 is the DOB of R. They can be represented as: D 1 = DD − MM −YY and D 2 = dd − mm − yy in the day, month, and year format.

a) S and R key generation
• S solves the two-component system (10) at time t and generates the equations (15) and (16) • R solves the two-component system (10) at time t and generates the Eq. (17) and (18) https://www.indjst.org/ b) Encryption and decryption message • S wants to send a message M to R secretly, he encrypts M using E(.) function given by (19) • When R receives a message from S and want to recover an original message M, he uses the D(.) function given by

Steganograph
In this part, we have to hide the secret message into cover image using LSB method. Consider a color image that we decomposed into 3 sub images component (Red, Green and Blue). Each pixel of components assumes a value between [0, 255] and represented with 8 bit. We replaced the least significant bit of some pixels of components by each bits of the secret message. This technic performed with good efficient because does not affect human perception.

Example
The Figure 11 shows  In the Figures 11 and 12, we observe that the cover image have the same visual aspect with stegano image. To see the difference between these images, we have to calculate the Peak Signal to Noise ratio (PSNR). The PSNR is given in (27) by Eq. (21).
The PSNR gives an objective measure of the distortion introduced by the steganography. It is expressed in decibels (dB). We found the PSNR of Lena and Flower equal to 59.28 dB and 62.01 dB respectively. Table 1 and Figure 13 show the evolution of PSNR between cover and stegano images according to length of secret message.
https://www.indjst.org/  Table 1 and Figure 13 show how the message length influence the quality of stegano image. We see that the proposed steganography algorithm achieves high stegano image quality.
In fact, in Table 1 and Figure 13, we observe the PSNR is maximum when the message length equal to 150. And when M increase, PSNR decrease slowly. This proof that our chaotic cipher adapted very well the LSB method for steganography.
The experimental results reveal the practicability and superiority of the presented technique.

Conclusion
In this work, we proposed a locally active memristor based on a current-controlled generic memristor that has two internal state variables-a second order memristor. The characteristics of the memristor were investigated and the memristor shown to have a wide locally active region and for properly chosen parameter values, the memristor can be switched from a predominantly passive region to an active region. A memristor-based chaotic circuit is presented, which only consists of a memristor and an inductor. The memristor model and the two component circuit were numerically simulated using MATLAB and the hardware implementation was designed using FPGA. The experimental results are consistent with the software simulations. For exploring https://www.indjst.org/ the potential application of the circuit, an application in steganography is included where we proposed a method to hide a secrete message inside an image using steganography and chaos encryption.