Minimization of power and area of digital modulator for cellular communication using cadence in 180nm, 90nm and 45nm CMOS technology

Background/Objectives: Low power modulators are most efficient for wireless communication. Quadrature Amplitude Modulation (QAM) is used widely for high data rate communication than BPSK and QPSK, since it carries more bits of information per symbol over the channel. The objective of this work is to minimize the power consumption and area utilization of 32-bit QAM modulator. Methods/Statistical analysis: In this work, three new procedures are introduced for 32QAM modulator. In the first approach, sine and cosine data generated using conventional technique are stored in ROM and the stored data is selected based on the input sequence to generate the output signal. This approach reduces the power consumption and area utilization. In the second approach, information bit stream ismodulated with sine and cosine waves generated by iterative algorithm to minimize power and area requirement. In the third approach, booth multiplication algorithm is employed to generate QAM signal. This method of generating QAM signal consumes less power and area in comparison with the conventional modulator. The work is synthesized, analyzed, and compared in 180nm, 90nm and 45nm CMOS technology using Cadence software. Findings: In 180nm CMOS technology power consumption noticed is 60662.740nW, 617020.071nW and 133679.687nW with the proposedmethod1,method2 andmethod3 respectively. An Area utilized in 180nm CMOS technology is 1341μm2, 20746.757μm2, and 2754μm2 respectively in proposed 32QAMmodulator with ROM, 32QAMmodulator with proposed Iterative algorithm and 32QAM modulator with Booth multiplication algorithm. Novelty/Applications: The conventional 32QAM devours additional power and area. In this work area and power reduction is achieved with respect to the conventional method. The same work is carried out with 90nm and 45nm CMOS technology. Three novel approaches to 32QAM are proposed. The proposed work is synthesized, analyzed, tabulated and compared with conventional method and shown that power consumption and area utilization are minimum than compared to the conventional method.


Introduction
Wireless networks are rapidly developing as an imperative advancement and turning in to a fundamental segment of contemporary day by day life. Digital modulation is used in numerous applications. Mobile radio communication has become an essential part of everyone's life. In order to increase the battery life of this electronic gadgets, the power and area reduction to be achieved through new techniques. Hence low power digital modulators are in demand.
Quadrature Amplitude Modulation (QAM) allows some considerable gains for the data transmission. As 16QAM transitions to 32QAM, 64QAM, 256QAM and onwards, more eminent information pace could be attainable by the side of the deprivation of noise margin. QPSK and QAM techniques are used to increase the capability and speed of wireless networks. Analog QAM is the combination of AM and PM. Digital QAM is the combination of ASK and PSK. In QAM modulation both amplitude and phase are modulated. The higher order of modulation permits to empower more bits/symbol. Information rate adaptability is maintained between channel considerations and modulation rate. If good signal to noise ratio is attainable, then higher order modulation is employed to achieve higher data rate at higher speed. In case of channel conditions are not meeting the appropriate signal to noise level, and then low information rate can be adaptable to ascertain low error rates (1)(2)(3)(4) . QAM can b e employed in various mobile radio and quality information delivery appliances. Direct to home (DTH), cable television applications transmit more information signals over the channel. This kind of application utilizes higher order modulation such as 64QAM and 256 QAM. Even though higher order modulators are proficient to provide high speed information signal pace and these are perceptibly minimum reluctant to distortion. (5)(6)(7)(8) .
The typical QPSK modulator demands Frequency synthesizer (DDS), adders, and multipliers to generate sine waveform. It requires adders, multipliers to generate a symbol with respect to input bit streams. As low power modulators are in demand for satellite and mobile radio networks, in this work, implantable QPSK modulator is developed, which requires less power for operation. The work is based on generating a symbol using data storage inside a memory block consorting to the incoming information streams. The work is modeled with Verilog hardware description language and Xilinx ISE (9,10) . Low power wide area networks problems are solved through innovative applications developed in recent years, In this work turbo Frequency shift keying is implemented, this FSK outputs the constant envelope waveform (11)(12)(13) . In the fourth generation networks, orthogonal frequency division multiplexing employed with Turbo-Frequency shift keying to obtain the constant envelope of the output signal. This improves the performance by minimizing error rate (14) .

Proposed Methods
Three new approaches are projected to 32 bit QAM modulator to achieve low power consumption and area reduction.
• Proposed 32QAM modulator with Memory • 32QAM modulator with proposed iterative algorithm: A new iterative algorithm is proposed to produce digital sine and cosine signals. This new approach for 32bit QAM digital modulator reduces the area and power consumption. • 32QAM modulator with Booth multiplication algorithm: A new approach is introduced for 32QAM modulators. In this work, the analog multiplication using product multiplier is replaced through the Booth multiplier. This results in reduction in area, gate utilization and minimizes the power consumption. The proposed work performance parameters such as area and power are compared with the existing work.

Proposed 32QAM with Memory
The conventional 32QAM modulator is shown in Figure 1. The three input bits in I-arm and two input bits in Q-arm are multiplied with the sine and cosine streams respectively. The multiplier output is added together to generate 32-QAM output. The sine and cosine data generated out of conventional method are stored in ROM as shown in Figure 2. The stored phase data is selected accordingly with the input bit streams.

Fig 2. Proposed QAM with ROM
The intended 32QAM modulator-3 is designated in Figure 3 below. It comprises of 6-bit register to store information bits, a register to store 6-bit address, a register to store control bits, multiplexer and adder. The real and imaginary data generated and added up to obtain digital 32QAM output.

32QAM with Proposed Iterative Algorithm
The flow chart shows the steps to generate sine and cosine using proposed algorithm as shown in Figure 4. Initially sine and cosine registers are declared and an initial data is stored in these registers. After satisfying the applied input conditions, the sine and cosine values are calculated as shown in Equation (1). The computed values are stored in sine_reg and cos_reg. The generated sine and cosine values are applied to the modulator block. An iterative algorithm is employed to generate digital sine and cosine signals as depicted below in Figure 4 and its implantation is shown in Figure 5.

32QAM with Proposed Iterative Algorithm
The flow chart is shown in Figure 6. Low power multipliers are highly demanded today. Most of the digital signal processing applications is based on arithmetic operations. They require high speed and low power multipliers. In this work, multiplication is carried out by using Booth multiplication, which in turn reduces the area and power in comparison with the typical design of 32bit qudrature amplitude modulator. The total power consumption is summation of static power and the dynamic power consumption. The significant power utilization is the dynamic power. While doing arithmetic operations, the power utilization primarily relied on the repetitive operations performed. In case of multiplication, power can be minimized through reducing the number of mathematical process. Numerous form of multipliers https://www.indjst.org/ are "Booth multiplier, combinational multiplier, Wallace tree Multiplier, array multiplier and sequential multiplier". The input message signal stream is renewed in to parallel data streams. This is stored multiplicand register. The carrier bit streams are stored in the multiplier register. The booth algorithm performs the signed multiplication of multiplicand and the multiplier. The "Booth algorithm" is employed to product two signed numbers. The signed numbers are in two's complement format. The binary information stream is converted into parallel bits of data. This data is the multiplicand and the multiplier are the digitized carrier signal. This multiplier is advantageous in terms of speed. If the transition bit and LSB of the input data is 10 and 01 then carrier data is subtracted and added to the product register, then arithmetic right shift is performed. If the transition bit and LSB of the input data is 00 or 11 then only arithmetic right shift is performed on product register. The counter is incremented each time till the input data stream reaches its maximum count. The implementation of 32QAM with multiplication method is represented in Figure 7.

Results and Discussion
The results of 32QAM modulators are compared. The analysis with respect to power and area utilization is carried out using Cadence software. Table 1 detail about leakage and dynamic power. The total power is the summation of dynamic and leakage power. The total power in nW and area in µm2 is represented in 180nm, 90nm and 45nm technology respectively. The total area utilized for this design is 1341µm2, 419µm2 and 125µm2 and the total power consumption is 60662.740nW, 15659.278nW and 3943.94nW in 180nm, 90nm and 45nm CMOS technology respectively.

Power and area analysis of 32QAM with iterative algorithm
The result of 32QAM modulator with iterative algorithm detailed in Table 2 below. Cadence Encounter(R) RTL Compiler RC13.10-v13.10-s006_1 is used for simulation and synthesis. The total power in nW and area in µm2 in 180nm, 90nm and 45nm technology is 617020.071nW, 156727.033nW and 14905.582nW and total area is 20746.757µm2, 6341µm2 and 966µm2 respectively.

Power and area analysis of 32QAM with Booth multiplication algorithm
The 32QAM with proposed method-3 is shown in Table 3 below. The total power consumed is 133679.687nW, 85601.465nW, 6452.911nW and the total area utilized is 2754µm 2 , 3075µm 2 and 214µm 2 in 180nm, 90nm and 45nm technology respectively.

Comparison and analysis of all proposed methods
The power and area report of all the three new approaches to 32QAM modulators are discussed compared and analyzed in 180nm, 90nm and 45nm CMOS technology using Cadence tool. The power and area reports are discussed below in Tables 4 and 5 respectively.

Power utilization report
The power consumed in all methods are compared and reported in Table 4 and the bar graph representation is depicted in Figure 8 below. As depicted in the figure below, the first approach consumes 60662.740nW, the second approach with iterative algorithm consumes 617020.071nW and the third proposed approach with Booth algorithm consumes 133679.687nW in 180nm technology. The power consumed in method1 in 90nm technology in 32QAM modulator with memory is 15659.278nW; with iterative algorithm is 156727.033nW and proposed 32QAM with method-3 is 85601.465nW respectively. In 45nm CMOS Technology, the first approach consumes 3943.94nW, second approach with iterative algorithm consumes 14905.582nW and the third proposed approach with Booth algorithm consumes 6452.911nW.

Area utilization Report
An area utilization and comparison is carried out using cadence synthesis tool in 180nm, 90nm and 45nm technology is reported below in Table 5. The area utilized in 180nm technology in method1, method2 and method3 is 1341µm 2 , 20746.757µm 2 , and 2754µm 2 respectively. https://www.indjst.org/ The area utilized in 90nm technology in method1, method2 and method3 is 419µm 2 , 6341µm 2 and 3075µm 2 respectively. The area utilized in 45nm technology in method1, method2 and method3 is 125µm 2 , 966µm 2 , and 214µm 2 respectively.  Table 5 is depicted with bar graph in Figure 9 below. The area utilized for 32QAM with iterative algorithm is maximum than the other two approaches. The proposed modulator-1 utilizes minimum area among other proposed methods. The area comparison report of all the three proposed 32QAM modulators in 180nm, 90nm and 45nm technology is represented in above figure.

Conclusion
In this study, new three approaches are discussed for 32QAM modulator. Area utilization and power consumption report is generated using cadence synthesis tool in 180nm, 90nm and 45nm technology. The proposed techniques for 32QAM system achieves effective concert in terms of area and power comparatively with typical way of designing 32QAM system with Direct Digital Frequency Synthesizer (DDFS). The proposed 32QAM modulator-1 consumes minimum power and utilizes minimum area compared with other proposed methods. The results are tabulated, analyzed and compared. The power consumption is much reduced in the proposed method in comparison with the existing work. The work is carried out in 180nm, 90nm and 45nm CMOS technology. The three novel approaches proposed in this work minimizes the power consumption and area utilization of 32QAM than compared to the conventional method. As the technology scales downs the area and power parameters are further minimized.

Acknowledgment
The author thanks JSS Academy of technical education, Bengaluru, Karnataka, India for providing Cadence lab facility to carry out this work.