RF Performance Evaluation of Nanoscale FD-SOI MOS Transistors

Objectives: In this work, the performance of single-gate and double-gate FD-SOI MOSFETs has been investigated in order to find out its utility RF applications. Methods/statistical analysis: The small-signal equivalent model is utilized to obtain the Y parameter of the devices and from which the minimum noise Figure and S parameter of the devices are derived and provides its applicability in the design of RFICs. The analysis is carried out using the Silvaco 2D ATLAS tool. Findings: The simplified small-signal equivalent models for both the devices are developed to analyze its high-frequency response more accurately, and to extract other important high-frequency (RF) parameters. Application/improvements: The derived S parameters are used to evaluate its high-frequency (RF) losses. In the SG FD-SOI MOSFET, the Insertion loss is 2.47 dB, the Transmission loss is 2.48 dB and the Reflection loss is 1.02 dB lower in comparison to DG FD-SOI MOSFET while its Return loss is 0.05 dB higher in comparison to that of DG FD-SOI MOSFET.


Introduction
The demand for high-performance wireless and RFIC applications with low power consumption is increasing day by day. This increasing demand leads to the need for very-high density on-chip integration in annexation with optimum performance. 1 To achieve these properties, the CMOS technology is clamped into the tenth of the nanometre range. 2 However, it becomes very arduous to preserve the behaviour of such semiconductor devices when its physical dimensions are reduced to a tenth of the nanometer range. The challenges arise due to the adverse effect imposed by the small geometry devices (SCEs). [3][4][5][6] To overcome the forestated hindrances, since last two decade researchers are making great effort and even various device designs already have been proposed. [7][8][9][10][11][12][13] SOI technology out of several MOS technology is preferred due to its several advantageous features like it highly suppress the leakage currents by using a buried oxide (BOX) insulating layer underneath the channel region and also its fabrication is easy and cost-efficient. [14][15][16][17] Considering the FD-SOI MOSFETs, In the Radiofrequency operating range several losses take place, so it is very essential to analyse these losses for more accuratecharacterization. 18 In the field of RF applications using FD-SOI MOS devices, a number of researches have already been carried out. [19][20][21][22] Lázaro & Iñiguez compares the RF/HF and noise behaviour of single-gate (SG) as well as double-gate (DG) FD-SOI MOS devices and found that f T of the DG SOI is greater in comparison to the SG-SOI and hence DG -OI has larger BW in comparison to the SG-SOI for RF applications 23 stated the impact of engineering in channel doping and gate electrode material on its analog & RF/HF performance of FD-SOI MOS device and obtained that gate engineered device has improved f T and f MAX while channel engineered device has reduced f T with respect to single metal double-gate (DG) MOSFET. 24 Later, in the DG MOS device the impact of gate electrode engineering on it is analog & RF/HF performance. The work concludes that the use of a triple metal gate electrode results in peak horizontal electric-field deviation at the source/ Keywords: FD-SOI MOSFET, RFICs, Leakage Current, Power Dissipation, RF Frequency channel interface region. This phenomenon improves the carrier transference efficiency and hence provides higher 1-decibel compression point when compared to that of the single metal DG and double metal DG MOSFET making it suitable device to achieve high linearity when used to design a ultra-wide band (UWB) LNA circuit 25 the influence of stacking high-k gate insulating dielectric material over a silicon dioxide material on RF/HF performance of the nanoscale DG FD-SOIMOSFET and concluded that gate stacking using Silicon Nitride (Si 3 N 4 ) as high-k dielectric material exhibit improved DIBL, reduced subthreshold slope (SS), better f T and gain as compared to that of the other high-k dielectric material making it primary choice for large BW analog and RF/HF applications. 26 The analog and RF analysis of the above-reported literature only deals with BW, short channel effects or power dissipation and their associated leakages. The losses in devices operating at the RF range have not been discussed by any of the earlier researchers. In this work, an investigation on the RF/HF performance of the single and double gate FD-SOI MOSFET is carried out combined with their associated high-frequency losses.
The key Figure-of-merits (FOMs) utilized for the RF/HF performance investigation of the MOS devices includes intrinsic capacitances (C gs & C gd ), cut-off or unity current gain frequency (f T ) and frequency transconductance gain product (FTGP). The results obtained for RF analysis of the designed devices have been compared & contrasted to that of the recently reported literature. Also, for the first time, a simplified small-signal high-frequency equivalent circuit model for the DG FD-SOI MOS device has been proposed to extract its essential RF/HF parameters.

Device Descriptions
The structure of both MOS devices is represented in Figures 1 and 2 respectively. Silicon dioxide (SiO 2 ) is used as an insulating material for the gate as well as for the buried-oxide (BOX) regions in both devices. 27 The source and drain diffusion regions are n-type regions doped with the Gaussian doping profile whereas the channel region is uniformly doped p-type region. The analysis is done by using a powerful Atlas 2D simulator. The physical model implemented for the MOS device simulation includes the common mobility model (CONMOB) to define the mobility of the device, for carrier recombination model, Shockley-Read-Hall (SRH) model is used and Boltzmann static (BOLTZMAN) as a static carrier transport model. 28 The physical parameters used in the designing of SG-and DG-FD-SOI MOS devices are described in Table 1.

Small Signal Analysis
The small signal analysis is essential to examine the RF/HF response of the MOSFETs more precisely and also to easily extract other important high-frequency parameters. 29,30 In the small signal analysis, the Source and Substrate (Body) terminal are shorted together in order to realize the effective configuration as a two-port network. This method is the simplest method used for extracting the parasitic components of the MOS devices which are utilized in accurate RF measurement. For common two port-networks, a particular current and voltage values are assigned to each of these ports. For a two-port analysis of the MOS devices, Source and Gate terminal are considered as an input port while the Source and Drain terminal is considered as an output port. For a two-port network if V 2 , I 2 and V 1 , I 1 are considered as voltages and currents at the output port and input port respectively, then it's short-circuited admittance parameter can be expressed as: The two-port admittance of the network is given by: These Y parameters can be utilized to obtain the effective S parameters which are further used for highfrequency analysis of the designed MOS devices. The Y parameters are used in the analysis because it is also known as the "Transadmittance parameter" i.e., voltagecontrolled current source (VCCS) and it is a known fact that the MOSFET is inherently the VCCS.
The high frequency small-signal equivalent circuit model for SG FD-SOI MOSFET 31 is shown in Figure 3 in which C gs , C gd , C sb , C db and C gb are the gate-to-source, gate-to-drain, source-to-body, drain-to-body and gateto-body capacitances respectively. The R s , R d , R g and R sub are the source, drain, gate and substrate resistances respectively.
The small-signal high-frequency equivalent circuit model for the representation of double gate FD-SOI MOSFET is shown in Figure 4 represents the high frequency in which gate-to-source capacitance (C gs ) is a combination of C g1s and C g2s , while gate-to-drain capacitance (C gd ) is a combination of C g1d and C g2d , C g1g2 is the capacitance between Gate1 and Gate2 terminals, R g1 and R g1 are the resistances across the Gate1 and Gate2 terminals respectively and R s , R d and R sub are the resistances across the source, drain and substrate terminals.
The C gd and C gs are due to overlapped structure of gate electrode on the drain as well as source diffusion regions which depend upon the height of the gate-electrode terminal and responsible for fringe capacitances at the source as well as drain edges. Both the maximum frequency of oscillation f max and the transition-frequency f T have an inverse relationship with all these capacitances and hence increase in capacitances results in a decrease in f T and f max . Therefore, the value of these capacitances required to be low in order to achieve better RF/HF behaviour. For distributed contact-resistance model, 32 the source and drain resistance is given by: where, R C represents the contact resistance, L S/D represents the length of the source or drain electrode (for symmetric MOSFET), W is the channel region width, the electron charge is q, N is doping concentration of source or drain diffusion region, t si represents the thickness of the silicon film and µ o is electron mobility under no bias condition.

Results and Discussions
The transfer characteristics for both SG and DG FD-SOI MOSFETs are obtained and shown here in Figure 5. For all the figures shown here, the line with square mark denotes the behaviour of SG FD-SOI MOSFET and the line having circular mark denotes the behaviour of DG FD-SOI MOSFET. The gradual increase in gate-to-source voltage results in a larger increase in the value of the drain current (I D ) in the DGMOS device in comparison to the SG MOS device. The leakage current in DG FD-SOI MOSFET is found to be 0.15 A/µm while it is equal to 0.09 A/µm in the single gate FD-SOI MOSFET. The Ion/ Ioff is 1.5 × 10 6 in double gate FD-SOI MOSFET and 10 3 in the SG MOS device. One can observe that the Ion/Ioff and the leakage current for the DG MOS device are larger which implies that it has high switching speed with high power dissipation. The intrinsic-capacitances (C gd and C gs ) of the devices are extracted by using small signal AC analysis after performing the DC analysis. In this work, the intrinsic capacitances (C gd and C gs ) are obtained by performing AC analysis at 1 MHz frequency with DC sweep voltage of 0V to 1.5V. Figure 6 represents the C gd and C gs variations at different gate-to-source voltages. For the double gate, FD-SOI MOSFET reduced value of both intrinsic capacitances (C gs and C gd ) are observed in comparison to that of the single-gate FD-SOI MOSFET. A smaller value of intrinsic capacitances implies that it has high transconductance value and hence it is more suitable for high-frequency applications.
The f T can be evaluated by using Eq. (7). In Figure 7, the value f T for DGFD-SOI MOSFET is found to be larger  in comparison to the SGFD-SOI MOSFET which reflects the higher gate electrode controllability over the channel with higher transconductance (g m ) value and with lower C gd and C gs as explained above.
Another key parameter for used in analog & RF/HF performance evaluation of the MOS devices is known as frequency transconductance gain product (FTGP) which is formulated in Eq. (8). FTGP shows the trade-off between switching speed and intrinsic voltage gain. For high-speed operation, we have to compromise with the voltage gain. When voltage gain increases, the lower limit of the drain current increases and the upper limit remains the same which shows that its Ion/Ioff ratio decreases and hence its switching speed decreases.

( )
T gs gd The variation of Y parameter (short circuit admittance parameter) with respect to the frequency up to 1 THz is represented from Figure 8-11. In Figures 8 and 9, it is clearly observed that Real (Y 11 ), Real (Y 22 ), Real (Y 12 ) and Real (Y 21 ) values for both the devices are frequencyindependent which implies that it is less sensitive to the high-frequency signals.
The variation of Img (Y 11 ), Img (Y 22 ), Img (Y 12 ) and Img (Y 21 ) values with respect to frequency for both the devices are shown in Figures 10 and 11. It is evident that the electrical characteristics exhibit by both the devices    is almost independent of the frequency up to several 100 GHz and beyond this, it changes abruptly. The plots for Y parameters reveal that both the devices are exhibit almost similar performance in terms of frequency sensitivity. Figure 12 represents the variation of minimumnoise Figure m for a different range of frequencies and it is observed that up to 100GHz of frequency range it is almost negligible and beyond this it increases abruptly. For single gate FD-SOI MOSFET, this increase is larger as compared to the double gate FD-SOI MOSFET. Figure 13-16 represents a variation of the S-parameters for different frequency ranges. The Y-parameters of the devices (Eq. (9) to Eq. (12)) 19 are utilized to derive the S-parameters. From the plot, it is observed that all the parameters are frequency-independent up to 10GHz of frequency range and beyond this, the change is gradual in nature. 11 In the high frequency operating range, several losses take place, so it is very essential to analyse these losses in order to characterize the device more accurately. Some    It is obtained that the leakage current in SGFD-SOI MOSFET is lower in comparison to the DGFD-SOI MOSFET which implies that the power-dissipation (static) in the former device is lower. The transconductance and Ion/Ioff ratio of the DG MOS device is greater than that of    the SGMOS device and implies that the DGMOS device is suitable for fast switching and large BW applications. Table 2 represents the RF/HF performance comparison of the designed MOS devices to that of the recently reported MOS devices. It is found that with decrease in the channel length, (0.25 µm in Ref. [31], 40 nm in Ref. [26] and 20 nm in this work) the value of g m increases due to which f T of the device also increases and follows the 1/L (L = channel length) trend, but in contrary to this it is found that the value of FTGP highly decreases which implies that the gain of the device decreases while switching speed increases.

Conclusion
An analysis of the RF/HF performance of the single and double-gate FD-SOI MOSFET is carried out. Also, the small signal equivalent circuits are developed in order to analyse the RF response of the device more accurately and to extract other important RF parameters.
The important FOMs used to investigate the RF/HF performance of the MOS devices are intrinsic C gs & C gd , f T and FTGP. It is observed that the value of g m for DGFD-SOI is 38% larger than that of SGFDOI, 97% larger than GSDGFD-SOI and 89% larger than SGFD-SOI. The f T for DGFD-SOI is 37% larger than that of SGFDOI, 99% larger than GSDGFD-SOI and 100% larger than SGFD-SOI. The leakage current in single gate FD-SOI MOSFET is 39% smaller in comparison to the double gate FD-SOI MOSFET which implies that the static-power dissipation in the former MOS device is lower. The Ion/Ioff ratio of the double gate FD-SOI MOSFET is 10 3 times greater than that of single gate FD-SOI MOSFET and implies that its switching speed is higher. The derived S parameters are used to evaluate its high-frequency losses. It is observed that in the SG FD-SOI MOSFET the Insertion loss is 2.47 dB, the Transmission loss is 2.48 dB and the Reflection loss is 1.02 dB lower than that of DG FD-SOI MOSFET while the Return loss is 0.05 dB higher as compared to that of DG FD-SOI MOSFET.