Design and Implementation of High Speed Viterbi Decoder and Convolution Encoder for SDR

Objectives: Data transmission in wireless communication system will be affected by noise. The Viterbi decoder and convolutional encoder are best suited for forward error detection and correcting codes for a channel.


Introduction
Convolutional codes are best suited for forward error correcting that has been extensively used in digital communication systems making transmission more reliable. To transfer data along a noisy channel, convolution codes offer good outcomes compared to block codes. Additional bits are given to input bit in convolutional encoding to reduce the probability of error. The effective technique for decoding the convolutional codes is viterbi decoder 1,2 . A Finite State Machine can be used to design the Convolution encoder. For each clock pulse, the encoder divides a single input bit into 2 or more bits corresponding to a polynomial generator. According to generator polynomial logic '1' denotes that there is connection between the stages and logic '0' denotes that there is no connection between the stages. The convolution encoder having a code rate of ½ is shown in Figure 1.
Using trellis diagram, state diagram and state table, convolutional encoder can be represented. The shift register content of the encoder represents the states Figure 1. State diagram and trellis diagram of convolution encoder are displayed in Figure 2(a) and 2(b) 3 . Trellis diagram is being used to decide the cumulative distances from the received input sequence to obtain similar transmissible sequence.

Viterbi Decoder
Viterbi decoding is known for implementing the technique of maximum likelihood decoding. The Viterbi decoder examines the complete received input sequence. The Viterbi decoder uses the Viterbi algorithm for decoding the bit stream which is encoded using a Convolutional code. The hard decision Viterbi decoding, uses hamming distance which depends on possibilities of 0 and 1. To determine the count of bits on the operation of x or gate, the hamming distance is used 4 .

Methodology
The Viterbi decoder comprised of following major block:

BMU
The purpose of the BM unit is to determine branch metric state values. The hard decision type decoder is taken using the hamming distance metric values are computed. It executes the EX-OR operation between each state's possible output symbol and the symbol received.

ACSU
The ACSU consists of Comparator, Multiplexer and adder.
The state metric is the sum of the minimum value of previous state metric at that state and current branch metric. Adder adds the previous state of the state metric and branch metric of the current state. At each state the state metric value is compared using comparator and multiplexer selects the state metric with the minimum value 5,6 .

PMU
PMU is the summation of the pervious iteration of path metric and the current input of the branch metric. At each node of trellis the partial path metric is computed and branch metric computed at the BMU is taken. The memory element stores the metric for next iteration and to find the path metric with minimum value at the last stage (iteration) of the trellis 7,8 .

TBU
TBU recognise the output and survivor path. The original bit given to the convolutional encoder is extracted by the trace back unit 9 .

The Computation of Hamming Distance Module
This module differentiates the obtained codes with the actual expected input codes of the current state in order to calculate the hamming distance between them. Figure  5 shows the schematic diagram for calculating the hamming distance.

Viterbi Algorithm
Viterbi algorithm is termed efficient algorithm as it reduces error possibilities 10 . The following three steps can explain the Viterbi algorithm briefly: 1. Trellis is weighed. Branch metrics are calculated. 2. In terms of the minimum path to n time, recursively calculate the minimum path to n-1 time. Procedure has been used in this step to repeatedly refresh the signal survivor path. This is called the recursion Add Compare Select (ACS). 3. Iteratively find the shortest distance that uses Step 2 decisions leads to each trellis state. Survivor path decoding finds the shortest path for the state. Lastly, the survivor paths incorporate the most likely signal path into a unique path when they are traced back in time. The flow chart for the Viterbi algorithm is shown in the Figure 6.

Result and Discussion
Matlab is used to determine, next state and output for the present state of convolutional encoder as shown in Figures 7 and 8.  The min and max values for next state and output is obtained as shown in Figure 9.      The timing utilization is obtained using Xilinx ISE14.1. The critical path delay, combinational path delay and also maximum and minimum time required before and after the clock for encoder and decoder is determined as shown in Tables 1 and 2. The Verilog HDL is used in Xilinx ISE 14.1 to design and synthesize the proposed architecture. The RTL schematic and timing summary for Viterbi decoder and convolutional encoder was obtained.

Conclusion
SDR is the technology for controlling radio performance through software.The design convolutional encoder and Viterbi decoder using trace back method and its performance characteristics in terms of, timing, summary and HDL synthesis report was successfully obtained. A bit of error was detected and corrected by the Viterbi decoder in the data input bit stream. The frequency of convolutional encoder is 1919.010 MHz and Viterbi decoder is 561.798 MHz. Thus, the implemented method where the speed is high, making the proposed architecture better suited for SDR applications with high speed.