Performance Analysis of BIST Algorithms

Objective: Performance analyses of March LR and March Care presented to achieve high fault coverage, low power dissipation, less area utilization and minimum testing time. Methods: Testing of memory consist of Built-In-Self-Test (BIST) controller and circuit-under-test. BIST algorithms are resided inside the BIST controller. BIST algorithms such as March LR and March Care coded in term of finite state machine. Memory is modeled in verilog and simulated in ModelSims for testing memory faults and it is synthesized by using Xilinx Vivado 2012.2 EDA tool for power, area and timing analysis. Findings: Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique. Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are Stuck-At Fault (SAF), Stuck Open Fault (SOF), Transition Fault (TF), Coupling Fault (CF) etc. These functional faults are model and write the code in verilog. Faults are inserted and detected using ModelSims. Using Xilinx Vivado 2012.2 EDA tool, power, area and timing are analyzed. Comparison is made between March Cand march LR. Even though March LR has more length (14N), it has high fault coverage and lesser power dissipation. Thus, March LR is more efficient than March C-. Applications/Improvements: The fault coverage is improved by using March LR. More improvement in March LR can detect more faults which result in the efficiency for online BIST


Introduction
Testing of memory is required to verify the correction of its hardware. The rapid growth in the field of semiconductor leads to increase the complexity of the memory structure exponentially 1,2 . The testing done by using Automatic Test Equipment (ATE) takes longer time and is expensive. To solve these challenges, technique known as Built-In-Self-Test (BIST) is introduced. In a study by 3 , "BIST is a design-for-test technique in which testing is accomplished through built-in-hardware features". In BIST method, extra components are implemented on the chip for testing itself. Test Pattern Generator (TPG), Circuit-Under-Test (CUT) and Output Response Analyzer (ORA) are the main components of basic BIST module. Figure 1 shows the simple BIST block diagram. TPG produces test pattern for locating particular address on CUT. The output data will be collected and verify by ORA from CUT which produces the result whether it is pass or fail. The whole operation is controlled by BIST Controller when the memory in testing mode.

BIST Algorithm for Memory Testing
Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique.
Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are as follow: There are so many memory faults are left to mention but for our performance analysis we are considering the above faults only.
Many BIST algorithms have been developed so far. March element may be operated in increasing, decreasing or either increasing or decreasing order depending of the algorithm. The operation may be writing operation or reading operation. Table 1 shows the various March Algorithms.
Where (↑) denotes increasing order of address, (↓) denotes decreasing order of address, (↕) denotes either increasing or decreasing order of address, (wb0 or wb1) indicates either writing a zero or one to a cell respectively, (rb0 or rb1) indicates either reading a zero or one from a cell respectively, N indicates no. of cells in the memory, AF indicates address fault, SAF indicates stuck-at fault, TF indicates transition fault, CF indicates coupling fault, CFid indicates idempotent coupling fault.
March based algorithm test gives high coverage faults and the testing time is usually linear with the size of the memory. In this paper, March Cand March LR will be analyzed.

Performance Analysis of BIST Algorithms
The March C-and March LR algorithms are considered for their performance analyses. For that 8 × 8 bit of memory is modeled in verilog and then simulated using ModelSim. Figure 2 & 3 shows the fault finding simulation for March LR algorithm. Fault finding simulation for March C-is also done in similar way.
For power, area and timing analysis, 1024x8 bit of memory is modeled using verilog and synthesized by using Xilinx Vivado 2012.2 EDA tool. The target device used for implementation is Virtex 7, XC7VX485TFFG1157-1. The power, area and maximum frequency reports are shown in Table 2.    March LR is much more efficient than the March Cas March LR used lesser power and lesser area utilization compared to that of March C-. But March C-has complexity of 10N where as March LR has complexity of 14N. So, March C-has lesser complexity.

Conclusion
This study is focused on the performance analysis of March algorithm such as March C-and March LR. It is concluded that March LR is more efficient than March C-. By modifying March LR algorithm, more BIST algorithm may be design for testing the memory in future.