NWR: Net Weighing Based Timing Driven Routing Algorithm

Objectives: Timing driven VLSI routing is a challenging problem considering that the number of interconnects in todays’ technology design nodes is growing rapidly. VLSI or FPGA global routing is difficult problem considering the complexity and large size of present day IC designs. Methods/Statistical analysis: Net weighing algorithms for timing driven placement are effective way of optimizing delays during routing of designs. Timing driven routing with net weighting approach has not been explored in the past. Findings: We present two novel timing driven routing algorithm which is based on weighting of the critical nets. In the first method slack of the net is considered in evaluating the criticality of the net, whereas, in the second method we consider exponent of the criticality of the pin. These weights are then applied to all the nets while performing timing driven global routing. Improvements: The results of our experiments are encouraging, wherein, we obtain an improvement of 17.38% and 22.35% over VPR in the weighing schemes called Method A and Method B respectively.


Introduction
As per the Moore's law gate count is increasing twice every year. With more number of cells added to a design, the complexity of placement and routing of a design also increases. It is the placement and routing of the designs that determine the delays and clock speed after the design is fabricated. To optimize the delay or clock period of the design, methods have been proposed at placement level as well as routing level. In this paper, we investigate the application of net weighing during the routing of FPGA based designs.
Timing optimization algorithms have been traditionally applied to placement problems. There are two types of approaches in the placement and routing methods: 1. Path based, and 2. Net based. In path based approaches, the critical path of the design under consideration are analyzed and optimized. These approaches are complex to analyze and difficult to implement which is primarily due to exponential number of paths in a design. Net based methods are easy to implement compare to path based approaches and hence are very popular. Weights of nets are computed based on the criticality of the net in the design, and then these weights are applied during the run of the routing tool.
Resources present in FPGA routing architecture use segments of various lengths. Due to this reason, the traditional (as in ASIC) methods of route length estimation do not apply. Timing driven routing becomes even more difficult under such scenario.
In this paper we investigate the net weighing schemes for FPGA based designs. Our approach in this paper is based on application of weights to the critical nets during the global routing flow. We use VPR tool for our experiments with a number of FPGA designs have proposed approximation algorithm for timing aware routing has been proposed in Kai Zhu et.al 1 . In their implementation they consider segments of routing resources present in the routing architecture of an FPGA. They explore the complexity of routing tree and present approximation algorithms as the solution. Di Wu et al 2 have proposed a timing driven routing approach which optimizes cou-pling capacitance related delays. In the unified graph model, they consider the coupling capacitance as well as the detour routing wire lengths. The problem is modeled as a Sequential Ordering Problem (SOP). Seokjin Lee et.al 3 use lagrangian relaxation based approach to timing driven routing for FPGA based designs. They use Lagrangian multipliers and sub-gradient projection method to guide the algorithm to form a routing tree. They also handle congestion constraints during global routing and produce results that outperform the state-of-the-art routing tools.
Shih Hsu et.al 4 proposes a method that optimizes crosstalk between routes along with the optimization of timing. After the initial timing driven routing run of the router, they form a delay degradation graph for adjacent wires on the die. Then, the delay degradation graph is iteratively improved by doing reassignment of the wires. They meet the goal of crosstalk constraints for all the nets in the design.
Yao-Wen Chang et.al 5 show that, in general, the timing driven routing problem is NP-complete. They also give approximation algorithms for this problem with guaranteed performance bound. They have considered a new model for timing driven routing in their implementation flow which is based on finding Minimum Spanning Tree (MST) with bounded delays. Xun Chen et.al 6 present two heuristics for the problem of dealing with high fan out nets during timing driven global routing.
Hanyu Liu et.al 7 has proposed a novel way of realizing of architecture of a design for FPGA which is time multiplexed. They analyze whether congestion problem can be solved by time-sharing a route, considering various nets of the routing channel in an FPGA. Kai Zhu et al 8 present an algorithm for determining nets with non-uniform upper bound. They have shown in their experiments that this algorithm can significantly improve routability and reduce delay bound violations.
Ramin Hojati et.al 9 present two methods to reduce resistivity minimization which are Topological Resistivity Minimization (TRM) and Constrained Resistivity Minimization (CRM). The idea behind their approach is to optimize the performance of the design by restricting the use of higher resistance layers. Some increase in the routing area is observed by them in their implementation.
Yan JT 10 presents a timing driven routing algorithm which tries to reduce the congestion in the routing resources. They exploit the flexibility improvement of the edges within the routing tree, to reduce routing and improve routability. They consider dynamic routing tree re-construction in their algorithm.
Zhaoyun Xing et.al 11 device a parallel algorithm for timing drives routing. Their algorithm minimizes the circuit area as well as the timing delay of the critical path.
In Section 2, we discuss the implementation aspects of the proposed routing tool. Experiments are presented in Section 3. Finally, we present the results of our approach in Section 3 which is followed by conclusion in Section 4.

Implementation of the Router
We implement timing driven routing for FPGA routing architecture. A typical FPGA routing architecture is show in Figure 1.
Our work is based on the framework of VPR. We implement net weighing algorithms within the framework of VPR. Source code of VPR is modified to implement net weighing schemes A and B. In method A, as shown in Figure 2, we traverse through all the nets of the design, which is followed by traversal for all the pins for each net. In line 1 we compute the Pin crit for each pin which is maximum of the ration of net slack divided by time period of the critical path of the design. Next, we assign Pin crit to be equal to 10 raised to the power of Pin crit . After this we choose the maximum of Max criticality and Pin crit .
In method B, as shown in Figure 3, in line 1 we assign Pin crit to be equal to Pin crit raised to the power of 10. After this we choose the maximum of Max criticality and Pin crit . Then we assign pin_criticality to variable Pin crit .

Experiments and Results
We carry out our experiments on twenty FPGA designs. The experiments are run on a 64-bit MAC running on UNIX operating system. We used VPR version 2.4 from internet.
The results obtained by using method A and method are shown in Table 1 and 2 respectively. As shown in Table 1, the third column represents the time period for each design, and column 4 and column 5 represent the time period obtained in timing analysis after running the router VPR and NWR respectively.
The comparison of time periods obtained for VPR and NWR (Method A and B) are shown in Figure 4 and 5 respectively. Note that while extracting the results for VPR we have used criticality exponent as 0.01 for VPR.

Conclusion
Timing driven routing is a well studied problem and important problem considering the impact of routing to performance of the design after fabrication. In this paper we present a timing driven routing algorithm. We present two methods for weighing the nets of critical path of a design. Our experiments show that an improvement of 17.38 % using Method A and 22.35% using Method B can be obtained. Our approach show promising results over well known FPGA routing tool VPR.